VDWALL A65 4K LED Video Wall Processor
The VDWALL A65 is a multi-screen splicing processor for LED installations that need 4K source handling, synchronized output and flexible screen geometry. It supports a 3840 × 2160 LED screen arrangement and allows individual output-image size, position and input cropping to be configured for the installation.
Inputs, Processing and Splicing
- Five 4K60 source inputs: three HDMI 2.0 and two DisplayPort 1.2 connections. Additional source options include the DVI-compatible input, SDI and CVBS connections listed below.
- 10-bit image processing, Faroudja de-interlacing and image enhancement, with seamless or fade transitions.
- Individual RGB saturation, grayscale and brightness adjustment with 256 levels.
- Automatic mosaic calculation from each screen section’s size and position.
- 13 display presets with mode copying and backup; front-panel, RS232, USB and LAN control.
Output Capacity and System Planning
Four DVI outputs provide a listed total driving capability of up to 9.2 million pixels. A single output allows a maximum width or height of 2160 pixels; the four outputs can extend to 8640 pixels in one dimension. These width and height limits are alternatives and must remain within the applicable format and total capacity.
For monitoring, a DVI output can feed a 1080p LCD to view the 4K input. Genlock supports synchronized cascading: the existing specification describes four A65 units for 8K4K at 60 Hz or 16K2K at 60 Hz. Consult the retained Genlock guide when planning this multi-device arrangement.
Technical Specifications
| Input | ||
|---|---|---|
| Amount / Type | 3×HDMI 2.0（VESA/CEA-861） 2×DP1.2（VESA） 1×CVBS 1×DVI（VESA/CEA-861）compatible with HDMI1.3a/VGA 1×SDI（SDI/HD-SDI/3G-SDI） | |
| CVBS Format | PAL/NTSC | |
| CVBS Impedance | 1V（p_p）/ 75Ω | |
| VGA Format | PC（VESA） | ≤1920×1200_60Hz |
| VGA Impedance | R、G、B = 0.7 V（p_p）/ 75Ω | |
| DVI Format | PC（VESA） | ≤1920×1200_60Hz |
| HDMIP Format（HDCP2.2） | PC（VESA） | ≤4096×2160_60Hz |
| HDMI2.0（CEA-861） | ||
| DP Format（HDCP2.2） | DisplayPort1.2（VESA） | ≤4096×2160_60Hz |
| SDI Format | SMPTE259M-C SMPTE 292M SMPTE 274M/296M SMPTE 424M/425M | 480i_60Hz 576i_50Hz 720p、1080i、1080p |
| Input Port | CVBS: BNC/ 75Ω DVI: 24+1 DVI_D HDMI: HDMI (Type A) DP: DP port SDI: BNC/ 75Ω | |
| Output | ||
| Type/Amount | 4×DVI | |
| DVI Format | 2160X1160_50Hz、2048X1200_50Hz、1920X1200_50Hz、 1920X1080_50Hz、1680X1440_50Hz、1440X1680_50Hz、 1200X1960_50Hz、1200x1600_60Hz、1440x1440_60Hz、1600x1344_60Hz、1920×1080_60Hz、2160x960_60Hz、 User defined resolution（Maximum 2160 pixels in width or height) | |
| Output Port | DVI：24+1 DVI_D | |
| Others | ||
| Control Ports | RS232/USB/LAN | |
| AC Power | 100-240V/AC 50/60Hz | |
| Power Consumption | 35W | |
| Ambient Temperature | 0-45 ℃ | |
| Ambient Humidity | 15-85% | |
| Dimension | 482.6(L) x 380(W) x 66.6(H)mm | |
| Package Dimension | 535(L) x 475(W) x 145(H)mm | |
| Weight | G.Weight：8.5Kg, N.Weight：6Kg | |
Frequently Asked Questions
Does the A65 accept 4K at 60 Hz?
Yes. It has three HDMI 2.0 and two DP 1.2 inputs for 4K60 sources; the input specification lists formats up to 4096 × 2160 at 60 Hz.
How many DVI outputs does the A65 provide?
There are four DVI outputs for synchronized splicing, with up to 9.2 million pixels listed for the overall processor.
Can each DVI output drive a 2160 × 2160 image?
The stated limit is 2160 pixels in width or height. It is not a specification for a 2160 × 2160 canvas; use the supported output formats in the table.
Can multiple A65 processors work in sync?
Yes. Genlock supports cascading. The four-device arrangements described on this page require the appropriate connections and setup in the Genlock PDF.
Can I preview a 4K input on a 1080p monitor?
Yes. The monitoring function allows a DVI output to connect to a 1080p LCD for monitoring the 4K input.
Product Images and Downloads
VDWALL A65 Series Multi-screen Splicing LED 4K Processor Overview
VDWALL A65 Series Multi-screen Splicing LED 4K Processor user quick setup guide
VDWALL A65 Series Multi-screen Splicing LED 4K Processor GenLock Description
